238 search results - page 11 / 48 » Hierarchical Interconnect Circuit Models |
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
- This paper presents a spectrally-weighted balanced truncation technique for RLC interconnects, a technique needed when the interconnect circuit parameters change as a result of v...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
— This paper describes an algorithm for generating provably passive reduced-order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to macromodel ...
AAAI
2006
13 years 9 months ago
2006
For many large systems the computational complexity of complete model-based diagnosis is prohibitive. In this paper we investigate the speedup of the diagnosis process by exploiti...
ICCAD
1996
IEEE
13 years 11 months ago
1996
IEEE
A methodology for hierarchicalstatistical circuit characterization which does not rely upon circuit-level Monte Carlo simulation is presented. The methodology uses principalcompon...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer siz...