238 search results - page 17 / 48 » Hierarchical Interconnect Circuit Models |
ISLPED
2003
ACM
14 years 26 days ago
2003
ACM
Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architec...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
CAD tools and research in the area of reduced-order modeling of largelinearinterconnect networkshaveevolved from merely finding a Pad´e approximation for the given network trans...
ICCAD
1997
IEEE
13 years 12 months ago
1997
IEEE
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monoton...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
This paper presents the sizing rules method for analog CMOS circuit design that consists of: first, the development of a hierarchical library of transistor pair groups as basic b...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
Abstract—The dynamic power consumed by a digital CMOS circuit is directly proportional to capacitance. In this paper, we consider pre-routing capacitance estimation for FPGAs and...