80 search results - page 9 / 16 » High level synthesis for reconfigurable datapath structures |
DAC
2003
ACM
14 years 9 months ago
2003
ACM
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
ISCAS
1999
IEEE
14 years 7 days ago
1999
IEEE
This paper presents the design consideration of high order digital AZ modulators used as modulus controller for fractional-N frequency synthesizer. A third-order MASH structure (M...
ISSS
2002
IEEE
14 years 27 days ago
2002
IEEE
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
A regular circuit structure called a River PLA and its reconfigurable version, Glacier PLA, are presented. River PLAs provide greater regularity than circuits implemented with sta...
FCCM
2011
IEEE
12 years 11 months ago
2011
IEEE
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...