733 search results - page 79 / 147 » High performance in tree-based parallel architectures |
HPDC
1997
IEEE
14 years 1 months ago
1997
IEEE
This paper describes PARDIS, a system containing explicit support for interoperability of PARallel DIStributed applications. PARDIS is based on the Common Object Request Broker Ar...
ISCA
2010
IEEE
13 years 7 months ago
2010
IEEE
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
VLSID
2001
IEEE
14 years 9 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
MICRO
2000
IEEE
13 years 8 months ago
2000
IEEE
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
CODES
2001
IEEE
14 years 16 days ago
2001
IEEE
Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy co...