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ISCAS
2007
IEEE
99views Hardware» more  ISCAS 2007»
14 years 1 months ago
A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints
— Hermitian Codes offer desirable properties such as large code lengths, good error-correction at high code rates, etc. The main problem in making Hermitian codes practical is to...
Rachit Agarwal, Emanuel M. Popovici, Brendan O'Fly...
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
14 years 22 days ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
CDC
2010
IEEE
181views Control Systems» more  CDC 2010»
13 years 2 months ago
Relationship between power loss and network topology in power systems
This paper is concerned with studying how the minimum power loss in a power system is related to its network topology. The existing algorithms in the literature all exploit nonline...
Javad Lavaei, Steven H. Low
ECMDAFA
2009
Springer
115views Hardware» more  ECMDAFA 2009»
14 years 2 months ago
Managing Flexibility: Modeling Binding-Times in Simulink
Abstract. Model-based development is supposed to improve the development efficiency by raising the abstraction level and generating applications instead of manually coding the appl...
Danilo Beuche, Jens Weiland
ICCAD
2004
IEEE
114views Hardware» more  ICCAD 2004»
14 years 4 months ago
High-level synthesis using computation-unit integrated memories
Abstract— High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data lay...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...