Sciweavers

1933 search results - page 382 / 387
» High-performance computing using accelerators
Sort
View
CASES
2006
ACM
14 years 1 months ago
Mitigating soft error failures for multimedia applications by selective data protection
With advances in process technology, soft errors (SE) are becoming an increasingly critical design concern. Due to their large area and high density, caches are worst hit by soft ...
Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, N...
CODES
2005
IEEE
14 years 1 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
SEM
2004
Springer
14 years 27 days ago
Service Discovery Protocol Interoperability in the Mobile Environment
The emergence of portable computers and wireless technologies has introduced new challenges for middleware. Mobility brings new requirements and is becoming a key characteristic. M...
Yérom-David Bromberg, Valérie Issarn...
RTSS
2003
IEEE
14 years 24 days ago
Data Caches in Multitasking Hard Real-Time Systems
Data caches are essential in modern processors, bridging the widening gap between main memory and processor speeds. However, they yield very complex performance models, which make...
Xavier Vera, Björn Lisper, Jingling Xue
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 19 days ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...