24 search results - page 4 / 5 » High-speed VLSI architecture for parallel Reed-Solomon decod... |
ENGL
2008
13 years 7 months ago
2008
This paper discusses novel dedicated hardware architecture for hybrid optimization based on Genetic algorithm (GA) and Simulated Annealing (SA). The proposed architecture achieves ...
ISCAS
2003
IEEE
14 years 19 days ago
2003
IEEE
A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to ...
FCCM
2008
IEEE
14 years 1 months ago
2008
IEEE
We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
Various calculation of matrices and vectors has been used in many digital signal processing systems. Although the calculation simply repeats multiplication and addition, the reite...
VLSID
2006
IEEE
14 years 1 months ago
2006
IEEE
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...