164 search results - page 15 / 33 » Implementation of a SliM Array Processor |
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...
DATE
2000
IEEE
13 years 11 months ago
2000
IEEE
This paper presents a single chip implementation of a space-time algorithm for co-channel interference (CCI) and intersymbol interference (ISI) reduction in GSM/DCS systems. The t...
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
—This paper presents a high-performance parallel context-based adaptive length coding (CAVLC) encoder implemented on a fine-grained many-core system. The software encoder is desi...
IJCNN
2008
IEEE
14 years 1 months ago
2008
IEEE
— In this work we show that a metaheuristic, the Variable Neighborhood Search (VNS), can be effectively used in order to improve the performance of the hardware–friendly versio...