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» Implementing a STARI chip
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ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
14 years 5 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
DATE
2009
IEEE
137views Hardware» more  DATE 2009»
14 years 3 months ago
A self-adaptive system architecture to address transistor aging
—As semiconductor manufacturing enters advanced nanometer design paradigm, aging and device wear-out related degradation is becoming a major concern. Negative Bias Temperature In...
Omer Khan, Sandip Kundu
MICRO
2007
IEEE
150views Hardware» more  MICRO 2007»
14 years 2 months ago
Leveraging 3D Technology for Improved Reliability
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
Niti Madan, Rajeev Balasubramonian
ISCAS
2006
IEEE
81views Hardware» more  ISCAS 2006»
14 years 2 months ago
Fully programmable bias current generator with 24 bit resolution per bias
This paper describes an on-chip programmable bias current generator, intended for mixed signal chips requiring a wide ranging set of currents. The individual generators share a ma...
Tobi Delbrück, Patrick Lichtsteiner
VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
14 years 2 months ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil