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DAC
2006
ACM
14 years 9 months ago
Novel full-chip gridless routing considering double-via insertion
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures. To improve via yield and reliability, redundant-via insertion is a highl...
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lum...
ICCAD
2004
IEEE
114views Hardware» more  ICCAD 2004»
14 years 5 months ago
High-level synthesis using computation-unit integrated memories
Abstract— High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data lay...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
SOSP
2005
ACM
14 years 5 months ago
Hibernator: helping disk arrays sleep through the winter
Energy consumption has become an important issue in high-end data centers, and disk arrays are one of the largest energy consumers within them. Although several attempts have been...
Qingbo Zhu, Zhifeng Chen, Lin Tan, Yuanyuan Zhou, ...
INFOVIS
2005
IEEE
14 years 2 months ago
PRISAD: A Partitioned Rendering Infrastructure for Scalable Accordion Drawing
We present PRISAD, the first generic rendering infrastructure for information visualization applications that use the accordion drawing technique: rubber-sheet navigation with gu...
James Slack, Kristian Hildebrand, Tamara Munzner
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 1 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...