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» Improvement of ASIC Design Processes
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103
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DAC
1997
ACM
15 years 7 months ago
Developing a Concurrent Methodology for Standard-Cell Library Generation
Abstract - This paper describes the development of a concurrent methodology for standard cell library generation. Use of a novel physical design automation method enables a high de...
Donald G. Baltus, Thomas Varga, Robert C. Armstron...
DATE
2010
IEEE
160views Hardware» more  DATE 2010»
15 years 8 months ago
Soft error-aware design optimization of low power and time-constrained embedded systems
— In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware d...
Rishad A. Shafik, Bashir M. Al-Hashimi, Krishnendu...
125
Voted
DATE
2008
IEEE
163views Hardware» more  DATE 2008»
15 years 9 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...
136
Voted
RECOMB
2004
Springer
16 years 3 months ago
Designing multiple simultaneous seeds for DNA similarity search
The challenge of similarity search in massive DNA sequence databases has inspired major changes in BLAST-style alignment tools, which accelerate search by inspecting only pairs of...
Yanni Sun, Jeremy Buhler
SIGCSE
2010
ACM
219views Education» more  SIGCSE 2010»
15 years 8 months ago
The design of an online environment to support pedagogical code reviews
Inspired by the formal code inspection process commonly used in the software industry, we have been exploring the use of pedagogical code reviews (PCRs), in which a team of three ...
Christopher D. Hundhausen, Anukrati Agrawal, Kyle ...