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ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
14 years 4 months ago
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
Shiyan Hu, Zhuo Li, Charles J. Alpert
MICRO
2009
IEEE
129views Hardware» more  MICRO 2009»
14 years 2 months ago
Execution leases: a hardware-supported mechanism for enforcing strong non-interference
High assurance systems such as those found in aircraft controls and the financial industry are often required to handle a mix of tasks where some are niceties (such as the contro...
Mohit Tiwari, Xun Li, Hassan M. G. Wassel, Frederi...
SIGMETRICS
1996
ACM
122views Hardware» more  SIGMETRICS 1996»
13 years 11 months ago
Experiments with Digital Video Playback
In this paper we describe our experiments on digital video applications, concentrating on the static and dynamic tradeo s involved in video playback. Our results were extracted fr...
Richard Gerber, Ladan Gharai
ISPD
2007
ACM
128views Hardware» more  ISPD 2007»
13 years 9 months ago
X-architecture placement based on effective wire models
In this paper, we derive the X-half-perimeter wirelength (XHPWL) model for X-architecture placement and explore the effects of three different wire models on X-architecture plac...
Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
14 years 7 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das