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TECS
2008
58views more  TECS 2008»
13 years 8 months ago
Improving SDRAM access energy efficiency for low-power embedded systems
Jelena Trajkovic, Alexander V. Veidenbaum, Arun Ke...
CASES
2007
ACM
14 years 16 days ago
A low power front-end for embedded processors using a block-aware instruction set
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
Ahmad Zmily, Christos Kozyrakis
DATE
2003
IEEE
141views Hardware» more  DATE 2003»
14 years 1 months ago
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...
Mahesh Mamidipaka, Nikil D. Dutt
CODES
2005
IEEE
13 years 10 months ago
An efficient direct mapped instruction cache for application-specific embedded systems
Caches may consume half of a microprocessor’s total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing...
Chuanjun Zhang
IPCCC
2006
IEEE
14 years 2 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John