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ISQED
2005
IEEE
76views Hardware» more  ISQED 2005»
14 years 3 months ago
Technology Mapping for Reliability Enhancement in Logic Synthesis
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
Zhaojun Wo, Israel Koren
DATE
2003
IEEE
141views Hardware» more  DATE 2003»
14 years 3 months ago
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...
Mahesh Mamidipaka, Nikil D. Dutt
DATE
2002
IEEE
94views Hardware» more  DATE 2002»
14 years 3 months ago
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis
This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...
Vivekananda M. Vedula, Jacob A. Abraham
ISCAS
2002
IEEE
201views Hardware» more  ISCAS 2002»
14 years 3 months ago
FGS+: optimizing the joint SNR-temporal video quality in MPEG-4 fine grained scalable coding
To enable video transmission over heterogeneous wireless networks, a highly scalable compression and streaming framework that can adapt to large and rapid bandwidth variations in ...
Raj Kumar Rajendran, Mihaela van der Schaar, Shih-...
ISCA
1998
IEEE
135views Hardware» more  ISCA 1998»
14 years 2 months ago
Confidence Estimation for Speculation Control
Modern processors improve instruction level parallelism by speculation. The outcome of data and control decisions is predicted, and the operations are speculatively executed and o...
Dirk Grunwald, Artur Klauser, Srilatha Manne, Andr...