174 search results - page 18 / 35 » Instruction Fetch Mechanisms for Multipath Execution Process... |
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
In this Paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, h...
FPGA
2004
ACM
14 years 26 days ago
2004
ACM
We describe an effort to prototype an Itanium microarchitecture using an FPGA. The microarchitecture model is written in the Bluespec hardware description language (HDL) and suppo...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
HPCC
2009
Springer
14 years 3 days ago
2009
Springer
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...