174 search results - page 26 / 35 » Instruction Fetch Mechanisms for Multipath Execution Process... |
MICRO
2003
IEEE
14 years 24 days ago
2003
IEEE
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
ICS
2001
Tsinghua U.
13 years 12 months ago
2001
Tsinghua U.
We describe the Slice Processor micro-architecture that implements a generalized operation-based prefetching mechanism. Operation-based prefetchers predict the series of operation...
IPPS
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract—Many studies have shown that load imbalancing causes significant performance degradation in High Performance Computing (HPC) applications. Nowadays, Multi-Threaded (MT1...
DAC
2010
ACM
13 years 7 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
MICRO
2008
IEEE
13 years 7 months ago
2008
IEEE
Distributed processors must balance communication and concurrency. When dividing instructions among the processors, key factors are the available concurrency, criticality of depen...