2784 search results - page 23 / 557 » Instruction Level Parallelism |
ASPDAC
2007
ACM
14 years 1 months ago
2007
ACM
In this Paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, h...
CODES
2003
IEEE
14 years 3 months ago
2003
IEEE
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
LCPC
2007
Springer
14 years 4 months ago
2007
Springer
Massively parallel SIMD array architectures are making their way into embedded processors. In these architectures, a number of identical processing elements having small private st...
DAC
1999
ACM
14 years 10 months ago
1999
ACM
We present a framework for rapidly exploring the design space of low power application-specific programmable processors (ASPP), in particular mediaprocessors. We focus on a catego...
EUROPAR
1997
Springer
14 years 2 months ago
1997
Springer
The shared cache structures and snoop cache structures for single-chip multiprocessors are evaluated and compared using an instruction level simulator. Simulation results show that...