29 search results - page 5 / 6 » Integrating BIST Techniques for On-Line SoC Testing |
DAC
2008
ACM
14 years 8 months ago
2008
ACM
In modular testing of system-on-a-chip (SoC), test access mechanisms (TAMs) are used to transport test data between the input/output pins of the SoC and the cores under test. Prio...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed. Extended frequ...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
The verification of modern computing systems has grown to dominate the cost of system design, often with limited success as designs continue to be released with latent bugs. This t...
DATE
2003
IEEE
14 years 22 days ago
2003
IEEE
Data correlation is a well-known problem that causes difficulty in VLSI testing. Based on a correlation metric, an efficient heuristic to select BIST registers has been proposed...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some seri...