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DATE
2000
IEEE
88views Hardware» more  DATE 2000»
13 years 12 months ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
ISSS
2000
IEEE
88views Hardware» more  ISSS 2000»
13 years 12 months ago
Experiments with the Peripheral Virtual Component Interface
The Peripheral Virtual Component Interface, or PVCI, is a standard intended to simplify the interfacing of peripheral cores to on-chip buses in a system-on-a-chip, by standardizin...
Roman L. Lysecky, Frank Vahid, Tony Givargis
ISSS
2000
IEEE
91views Hardware» more  ISSS 2000»
13 years 12 months ago
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
Tony Givargis, Frank Vahid, Jörg Henkel
DATE
1999
IEEE
162views Hardware» more  DATE 1999»
13 years 11 months ago
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
Robert P. Dick, Niraj K. Jha
ICCAD
1996
IEEE
133views Hardware» more  ICCAD 1996»
13 years 11 months ago
Basic concepts for an HDL reverse engineering tool-set
Designer's productivity has become the key-factor of the development of electronic systems. An increasing application of design data reuse is widely recognized as a promising...
Gunther Lehmann, Bernhard Wunder, Klaus D. Mü...