154 search results - page 8 / 31 » Interconnect Optimization Strategies for High-Performance VL... |
DATE
2003
IEEE
14 years 3 months ago
2003
IEEE
Circuit marginality failures in high performance VLSI circuits are projected to increase due to shrinking process geometries and high frequency design techniques. Capacitive cross...
ISCAS
1999
IEEE
14 years 2 months ago
1999
IEEE
High-level power design presents a complex, multiobjective problem that involves the simultaneous optimisation of competing criteria such as speed, area and power. It is difficult...
ICCAD
1997
IEEE
14 years 2 months ago
1997
IEEE
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends...
TVLSI
2008
13 years 10 months ago
2008
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
GLVLSI
2009
IEEE
14 years 5 months ago
2009
IEEE
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...