54 search results - page 5 / 11 » Interconnect design for deep submicron ICs |
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need for analyzing logic...
DAC
1999
ACM
13 years 11 months ago
1999
ACM
Buffer insertion has become a critical step in deep submicron design, and several buffer insertion/sizing algorithms have been proposed in the literature. However, most of these m...
DSN
2006
IEEE
14 years 19 days ago
2006
IEEE
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are ...
ASPDAC
2004
ACM
14 years 20 hour ago
2004
ACM
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one...
ISPD
1998
ACM
13 years 10 months ago
1998
ACM
This paper describes an important new facility for timing-driven design applications within the new CHDStd standard for a SEMATECH design system for large complex chips. We first ...