54 search results - page 8 / 11 » Interconnect design for deep submicron ICs |
ASPDAC
1999
ACM
13 years 11 months ago
1999
ACM
Certain manufacturing steps in very deep submicron VLSI involve chemical-mechanical polishing CMP which has varying e ects on device and interconnect features, depending on loca...
ICCAD
2006
IEEE
14 years 3 months ago
2006
IEEE
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
ICCAD
2001
IEEE
14 years 3 months ago
2001
IEEE
In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. T...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
: Scaling down in very deep submicron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high perform...
DAC
2003
ACM
14 years 7 months ago
2003
ACM
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...