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» Interconnect design methods for memory design
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ISCA
2011
IEEE
258views Hardware» more  ISCA 2011»
12 years 11 months ago
A case for heterogeneous on-chip interconnects for CMPs
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...
Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. ...
ASPDAC
2006
ACM
91views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Statistical corner conditions of interconnect delay (corner LPE specifications)
- Timing closure in LSI design becomes more and more difficult. But the conventional interconnect RC extraction method have over-margins caused by its corner conditions settings. I...
Kenta Yamada, Noriaki Oda
CODES
2009
IEEE
14 years 2 months ago
An on-chip interconnect and protocol stack for multiple communication paradigms and programming models
A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The d...
Andreas Hansson, Kees Goossens
DAC
2000
ACM
14 years 8 months ago
Performance analysis and optimization of latency insensitive systems
Latency insensitive design has been recently proposed in literature as a way to design complex digital systems, whose functional behavior is robust with respect to arbitrary varia...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...
ISLPED
2005
ACM
96views Hardware» more  ISLPED 2005»
14 years 1 months ago
Power-optimal repeater insertion considering Vdd and Vth as design freedoms
This work first presents an analytical repeater insertion method which optimizes power under delay constraint for a single net. This method finds the optimal repeater insertion ...
Yu Ching Chang, King Ho Tam, Lei He