Sciweavers

731 search results - page 20 / 147
» Interconnect modeling for improved system-level design optim...
Sort
View
ISLPED
2005
ACM
96views Hardware» more  ISLPED 2005»
14 years 1 months ago
Power-optimal repeater insertion considering Vdd and Vth as design freedoms
This work first presents an analytical repeater insertion method which optimizes power under delay constraint for a single net. This method finds the optimal repeater insertion ...
Yu Ching Chang, King Ho Tam, Lei He
ASPDAC
2010
ACM
137views Hardware» more  ASPDAC 2010»
13 years 5 months ago
Improved on-chip router analytical power and area modeling
Over the course of this decade, uniprocessor chips have given way to multi-core chips which have become the primary building blocks of today's computer systems. The presence o...
Andrew B. Kahng, Bill Lin, Kambiz Samadi
ICCAD
1997
IEEE
134views Hardware» more  ICCAD 1997»
13 years 11 months ago
Post-route optimization for improved yield using a rubber-band wiring model
This paper presents a unique approach to improve yield given a routed layout. Currently after routing has been completed and compacted, it generally proceeds to verification witho...
Jeffrey Z. Su, Wayne Wei-Ming Dai
GLVLSI
1996
IEEE
125views VLSI» more  GLVLSI 1996»
13 years 11 months ago
Performance-Driven Interconnect Global Routing
In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacit...
Dongsheng Wang, Ernest S. Kuh
DAC
2002
ACM
14 years 8 months ago
HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery
This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we devel...
Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, Charlie Ch...