731 search results - page 68 / 147 » Interconnect modeling for improved system-level design optim... |
EICS
2010
ACM
13 years 5 months ago
2010
ACM
We propose an automated routine for hierarchical menu structure optimization. A computer advice-giving system founded on the mathematical model of menu navigation directs the desi...
ISCAS
1999
IEEE
14 years 42 min ago
1999
IEEE
- Micromachined power sensors with operation up to 50 GHz were recently achieved in CMOS technology [1]. To improve their sensitivity and signal-to-noise ratio, while maintaining m...
FPGA
2003
ACM
14 years 28 days ago
2003
ACM
This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contri...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Among the many techniques for system-level power management, it is not currently possible to guarantee timing constraints and have a comprehensive system model at the same time. S...