28 search results - page 2 / 6 » Iterative remapping for logic circuits |
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...
ITC
2003
IEEE
14 years 22 days ago
2003
IEEE
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
CSL
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. By introducing a parallel extension rule that is aware of independence of the introduced extension variables, a calculus for quantified propositional logic is obtained w...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the cl...
ICCAD
2000
IEEE
13 years 12 months ago
2000
IEEE
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...