129 search results - page 23 / 26 » Layout synthesis for datapath designs |
ASPDAC
2007
ACM
14 years 17 days ago
2007
ACM
In a realistic design flow, circuit and system optimizations must interact with physical aspects of the design. For example, improvements in timing and power may require replacing ...
ICCAD
2002
IEEE
14 years 5 months ago
2002
IEEE
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
—The growing trend towards using component based design approach in embedded system development requires addressing newer system engineering challenges. These systems are usually...