129 search results - page 3 / 26 » Layout synthesis for datapath designs |
ICES
2003
Springer
14 years 20 days ago
2003
Springer
This paper presents a methodology to design optimized electronic systems from high abstraction level descriptions. The methodology uses Genetic Programming in addition to high-leve...
DAC
2012
ACM
11 years 9 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
DAC
1999
ACM
13 years 11 months ago
1999
ACM
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
DATE
2002
IEEE
14 years 12 days ago
2002
IEEE
This paper describes the AccuPower toolset -- a set of simulation tools accurately estimating the power dissipation within a superscalar microprocessor. AccuPower uses a true hard...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...