129 search results - page 9 / 26 » Layout synthesis for datapath designs |
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling a...
ISSS
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—This paper presents a technique to perform arbitrary fixed permutations on streaming data. We describe a parameterized architecture that takes as input n data points st...
DAC
1996
ACM
13 years 11 months ago
1996
ACM
To reduce the number of synthesis and layout iterations, we present a new delay optimization technique, which inserts buers based on back-annotated detailed routing information. D...