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ISCAS
2007
IEEE
96views Hardware» more  ISCAS 2007»
14 years 1 months ago
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks
— Fast addition and multiplication are of paramount importance in many arithmetic circuits and processors. The use of redundant number system for efficient implementation of thes...
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingam...
GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
14 years 20 days ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
13 years 12 months ago
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
Lorena Anghel, Michael Nicolaidis
ICES
2003
Springer
108views Hardware» more  ICES 2003»
14 years 23 days ago
A Morphogenetic Evolutionary System: Phylogenesis of the POEtic Circuit
Abstract. This paper describes a new evolutionary mechanism developed specifically for cellular circuits. Called morphogenetic system, it is inspired by the mechanisms of gene exp...
Daniel Roggen, Dario Floreano, Claudio Mattiussi
VTS
2006
IEEE
108views Hardware» more  VTS 2006»
14 years 1 months ago
Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing
Abstract— Numerous machine-learning-based test methodologies have been proposed in recent years as a fast alternative to the standard functional testing of mixed-signal/RF integr...
Haralampos-G. D. Stratigopoulos, Yiorgos Makris