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ICCAD
1999
IEEE
77views Hardware» more  ICCAD 1999»
13 years 11 months ago
Symbolic functional and timing verification of transistor-level circuits
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaust...
Clayton B. McDonald, Randal E. Bryant
DATE
2009
IEEE
123views Hardware» more  DATE 2009»
13 years 10 months ago
Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis
This paper exploits the unique in-field controllability of the device polarity of ambipolar carbon nanotube field effect transistors (CNTFETs) to design a technology library with ...
M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De ...
DATE
2010
IEEE
170views Hardware» more  DATE 2010»
14 years 21 hour ago
Analytical model for TDDB-based performance degradation in combinational logic
With aggressive gate oxide scaling, latent defects in the gate oxide manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred...
Mihir Choudhury, Vikas Chandra, Kartik Mohanram, R...
ICCAD
1996
IEEE
151views Hardware» more  ICCAD 1996»
13 years 11 months ago
Expected current distributions for CMOS circuits
The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper...
Dennis J. Ciplickas, Ronald A. Rohrer
ARCS
2004
Springer
14 years 10 days ago
Reconfigurable OPTO-ASICs as base for future self-organizing CMOS cameras
: We investigated different parallel SIMD (single instruction multiple data) architectures based on pure programmable and reconfigurable approaches for their appropriateness for in...
Dietmar Fey, Daniel Schmidt 0003, Andreas Loos