233 search results - page 16 / 47 » Logic design for low-voltage low-power CMOS circuits |
DAC
2004
ACM
14 years 2 months ago
2004
ACM
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feed...
GLVLSI
2002
IEEE
14 years 1 months ago
2002
IEEE
A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
ISCAS
2005
IEEE
14 years 2 months ago
2005
IEEE
— There is a growing interest in developing low cost, low power, highly integrated biosensor systems to characterize individual cells for applications such as cell analysis, drug...
ICCD
2005
IEEE
14 years 5 months ago
2005
IEEE
: Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes are adopted to reduce...