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» Logic design for low-voltage low-power CMOS circuits
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ATS
2005
IEEE
164views Hardware» more  ATS 2005»
13 years 10 months ago
A Family of Logical Fault Models for Reversible Circuits
Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional ...
Ilia Polian, Thomas Fiehn, Bernd Becker, John P. H...
GECCO
2004
Springer
182views Optimization» more  GECCO 2004»
14 years 2 months ago
On the Evolution of Analog Electronic Circuits Using Building Blocks on a CMOS FPTA
This article summarizes two experiments utilizing building blocks to find analog electronic circuits on a CMOS Field Programmable Transistor Array (FPTA). The FPTA features 256 pr...
Jörg Langeheine, Martin Trefzer, Daniel Br&uu...
ISCAS
2002
IEEE
94views Hardware» more  ISCAS 2002»
14 years 1 months ago
A robust self-resetting CMOS 32-bit parallel adder
This paper presents new circuit configurationsfor a more robust and efficient form of self-resettingCMOS (SRCMOS). Prior structures for SRCMOS have very high performance but are...
Gunok Jung, V. A. Sundarajan, Gerald E. Sobelman
ICCAD
2010
IEEE
133views Hardware» more  ICCAD 2010»
13 years 6 months ago
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs
Coarse-grain multi-threshold CMOS (MTCMOS) is an effective power-gating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS power switc...
Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia...
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
14 years 9 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty