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» Logic design for low-voltage low-power CMOS circuits
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CF
2005
ACM
13 years 10 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
DAC
1994
ACM
14 years 23 days ago
The Design of High-Performance Microprocessors at Digital
Today's high-performance single-chip CMOS microprocessors are the most complex and challenging chip designs ever implemented. To stay on the leading edge, Digital's micro...
Thomas F. Fox
ISQED
2005
IEEE
125views Hardware» more  ISQED 2005»
14 years 2 months ago
A New Method for Design of Robust Digital Circuits
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...
DAC
2010
ACM
13 years 12 months ago
SRAM-based NBTI/PBTI sensor system design
NBTI has been a major aging mechanism for advanced CMOS technology and PBTI is also looming as a big concern. This work first proposes a compact on-chip sensor design that tracks ...
Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. W...
ISPD
1999
ACM
128views Hardware» more  ISPD 1999»
14 years 29 days ago
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
Michael A. Riepe, Karem A. Sakallah