233 search results - page 43 / 47 » Logic design for low-voltage low-power CMOS circuits |
DAC
2003
ACM
14 years 9 months ago
2003
ACM
As CMOS technology continues its monotonic shrink, computing with quantum dots remains a goal in nanotechnology research. Quantum-dot cellular automata (QCA) is a paradigm for low...
ISLPED
2005
ACM
14 years 2 months ago
2005
ACM
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
DAC
2004
ACM
14 years 9 months ago
2004
ACM
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...