Sciweavers

52 search results - page 2 / 11
» Low Power BIST Based on Scan Partitioning
Sort
View
ITC
2000
IEEE
55views Hardware» more  ITC 2000»
13 years 12 months ago
Low power BIST design by hypergraph partitioning: methodology and architectures
Patrick Girard, Christian Landrault, Loïs Gui...
ITC
1997
IEEE
93views Hardware» more  ITC 1997»
13 years 11 months ago
Fault Diagnosis in Scan-Based BIST
A deterministic-partitioning technique and an improved analysis scheme for fault diagnosis in Scan-Based BIST is proposed. The incorporation of the superposition principle to the ...
Janusz Rajski, Jerzy Tyszer
DFT
2003
IEEE
100views VLSI» more  DFT 2003»
14 years 23 days ago
Scan-Based BIST Diagnosis Using an Embedded Processor
For system-on-chip designs that contain an embedded processor, this paper present a software based diagnosis scheme that can make use of the processor to aid in diagnosis in a sca...
Kedarnath J. Balakrishnan, Nur A. Touba
DFT
1999
IEEE
131views VLSI» more  DFT 1999»
13 years 11 months ago
Optimal Vector Selection for Low Power BIST
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaud...