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» Low Power BIST Based on Scan Partitioning
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ICCD
2004
IEEE
109views Hardware» more  ICCD 2004»
14 years 4 months ago
Low Power Test Data Compression Based on LFSR Reseeding
Many test data compression schemes are based on LFSR reseeding. A drawback of these schemes is that the unspecified bits are filled with random values resulting in a large number ...
Jinkyu Lee, Nur A. Touba
VTS
2005
IEEE
89views Hardware» more  VTS 2005»
14 years 1 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
VLSID
2007
IEEE
130views VLSI» more  VLSID 2007»
14 years 7 months ago
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
The Discrete Wavelet Transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall ...
Rahul Jain, Preeti Ranjan Panda
ASYNC
2005
IEEE
112views Hardware» more  ASYNC 2005»
14 years 1 months ago
Request-Driven GALS Technique for Wireless Communication System
A Globally Asynchronous - Locally Synchronous (GALS) technique for application in wireless communication systems is proposed and evaluated. The GALS wrappers are based on a reques...
Milos Krstic, Eckhard Grass, Christian Stahl
DDECS
2007
IEEE
201views Hardware» more  DDECS 2007»
14 years 1 months ago
Built in Defect Prognosis for Embedded Memories
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskaran...