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DAC
2001
ACM
16 years 7 months ago
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems
Power-aware systems are those that must make the best use of available power. They subsume traditional low-power systems in that they must not only minimize power when the budget ...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi ...
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
16 years 19 days ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie
ICCAD
2002
IEEE
163views Hardware» more  ICCAD 2002»
16 years 3 months ago
Sub-90nm technologies: challenges and opportunities for CAD
Future high performance microprocessor design with technology scaling beyond 90nm will pose two major challenges: (1) energy and power, and (2) parameter variations. Design practi...
Tanay Karnik, Shekhar Borkar, Vivek De
HPCA
2003
IEEE
16 years 6 months ago
Power-Aware Control Speculation through Selective Throttling
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...
Juan L. Aragón, José González...
DATE
2003
IEEE
127views Hardware» more  DATE 2003»
15 years 11 months ago
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Amit Agarwal, Kaushik Roy, T. N. Vijaykumar