1307 search results - page 33 / 262 » Low Power Hardware for a High Performance PDA |
ISLPED
2000
ACM
13 years 12 months ago
2000
ACM
In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Variou...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Given a set of real-time tasks scheduled using the earliest deadline first (EDF) algorithm, we discuss two techniques for reducing power consumption while meeting all timing requi...
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
- Each year tens of billions of Dollars are wasted by the microelectronics industry because of missed deadlines and delayed design projects. These delays are partially due to desig...
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and im...
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
With the increasing clock rate and transistor count of today's microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and po...