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CORR
2007
Springer
112views Education» more  CORR 2007»
15 years 6 months ago
On Optimum Power Allocation for the V-BLAST
—A unified analytical framework for optimum power allocation in the unordered V-BLAST algorithm and its comparative performance analysis are presented. Compact closed-form appro...
Victoria Kostina, Sergey Loyka
DSD
2007
IEEE
160views Hardware» more  DSD 2007»
16 years 12 days ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire
MICRO
2008
IEEE
79views Hardware» more  MICRO 2008»
15 years 6 months ago
Strategies for mapping dataflow blocks to distributed hardware
Distributed processors must balance communication and concurrency. When dividing instructions among the processors, key factors are the available concurrency, criticality of depen...
Behnam Robatmili, Katherine E. Coons, Doug Burger,...
DATE
2006
IEEE
171views Hardware» more  DATE 2006»
16 years 4 days ago
Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off
We present a dynamic bit-width adaptation scheme in DCT applications for efficient trade-off between image quality and computation energy. Based on sensitivity differences of 64 ...
Jongsun Park, Jung Hwan Choi, Kaushik Roy
FPGA
2000
ACM
128views FPGA» more  FPGA 2000»
15 years 9 months ago
Factoring large numbers with programmable hardware
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...
Hea Joung Kim, William H. Mangione-Smith