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» Low Power Testing of VLSI Circuits: Problems and Solutions
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VLSID
2007
IEEE
142views VLSI» more  VLSID 2007»
14 years 8 months ago
Controllability-driven Power Virus Generation for Digital Circuits
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...
K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekanan...
GLVLSI
2008
IEEE
204views VLSI» more  GLVLSI 2008»
14 years 2 months ago
NBTI resilient circuits using adaptive body biasing
Reliability has become a practical concern in today’s VLSI design with advanced technologies. In-situ sensors have been proposed for reliability monitoring to provide advance wa...
Zhenyu Qi, Mircea R. Stan
VLSID
2002
IEEE
107views VLSI» more  VLSID 2002»
14 years 8 months ago
Estimation of Maximum Power-Up Current
Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-...
Fei Li, Lei He, Kewal K. Saluja
GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
14 years 21 days ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi
VLSID
2003
IEEE
103views VLSI» more  VLSID 2003»
14 years 8 months ago
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...