173 search results - page 7 / 35 » Low power and low voltage CMOS digital circuit techniques |
VLSID
2001
IEEE
14 years 8 months ago
2001
IEEE
Development of the process technology for dual threshold (dual Vth ) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance ...
ISVLSI
2002
IEEE
14 years 19 days ago
2002
IEEE
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...
ISLPED
2000
ACM
14 years 2 days ago
2000
ACM
Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented cir...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract— This paper reports the design of a high performance, adaptive low/high swing CMOS driver circuit (mj–driver) suitable for driving of global interconnects with large c...
ESSCIRC
2011
12 years 7 months ago
2011
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...