331 search results - page 17 / 67 » Low power implementation of a turbo-decoder on programmable ... |
185
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CODES
2004
IEEE
15 years 9 months ago
2004
IEEE
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
150
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ASAP
2003
IEEE
15 years 11 months ago
2003
IEEE
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
154
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ISCAS
2006
IEEE
15 years 12 months ago
2006
IEEE
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
160
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VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The systemlev...
161
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DAC
1999
ACM
15 years 10 months ago
1999
ACM
High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs. The problem is that domino logic comes at a...