21 search results - page 1 / 5 » Low power sequential circuit design by using priority encodi... |
ISLPED
2000
ACM
14 years 2 months ago
2000
ACM
This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. Th...
DATE
2006
IEEE
14 years 5 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
DATE
2005
IEEE
14 years 4 months ago
2005
IEEE
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
ARVLSI
1995
IEEE
14 years 2 months ago
1995
IEEE
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...
ISLPED
1995
ACM
14 years 2 months ago
1995
ACM
This paper presents an e ective multiple clocking scheme for lower power RTL circuit design. The basis is to partition a behavioral description of the circuit into m modules fed b...