552 search results - page 17 / 111 » Low power techniques for Motion Estimation hardware |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation....
ISLPED
2000
ACM
13 years 11 months ago
2000
ACM
This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. Th...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
This paper describes a procedure for minimizing the power consumption in a boolean network under the zero delay model. Power is minimized by modifying the function of each interme...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume lit...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
— Power gating is a circuit technique that enables high performance and low power operation. One of the challenges in power gating is sizing the sleep transistor which is used to...