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» Low power techniques for Motion Estimation hardware
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ISLPED
1995
ACM
235views Hardware» more  ISLPED 1995»
15 years 9 months ago
Low power and EMI, high frequency, crystal oscillator
The high-frequency oscillator is one of the major causes of both high power consumption and high ElectroMagnetic Interference (EMI) in Embedded Systems (ES). This paper presents a...
Rafael Fried, Reuven Holzer
ICCD
2002
IEEE
115views Hardware» more  ICCD 2002»
16 years 2 months ago
Low-Power, High-Speed CMOS VLSI Design
Ubiquitous computing is a next generation information technology where computers and communications will be scaled further, merged together, and materialized in consumer applicati...
Tadahiro Kuroda
ICCAD
1996
IEEE
131views Hardware» more  ICCAD 1996»
15 years 9 months ago
Multi-level logic optimization for low power using local logic transformations
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
Qi Wang, Sarma B. K. Vrudhula
VTS
1998
IEEE
124views Hardware» more  VTS 1998»
15 years 10 months ago
A Test Pattern Generation Methodology for Low-Power Consumption
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
ASPDAC
2005
ACM
90views Hardware» more  ASPDAC 2005»
15 years 7 months ago
Register placement for low power clock network
In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated...
Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qian...