877 search results - page 91 / 176 » MXQuery with Hardware Acceleration |
120
Voted
DDECS
2009
IEEE
15 years 9 months ago
2009
IEEE
—Automatic Test Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. Boolean solvers wor...
112
Voted
DATE
2008
IEEE
15 years 9 months ago
2008
IEEE
We present an efficient analog synthesis algorithm employing regression models of circuit matrices. Circuit matrix models achieve accurate and speedy synthesis of analog circuits...
105
Voted
DATE
2007
IEEE
15 years 9 months ago
2007
IEEE
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable com...
117
Voted
DDECS
2007
IEEE
15 years 9 months ago
2007
IEEE
This paper proposes debug patterns combined with an intuitive flow to accelerate and simplify the debugging of SystemC designs. A debug pattern provides a formalized procedure to f...
110
Voted
FCCM
2006
IEEE
15 years 8 months ago
2006
IEEE
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony’s Playstation 2 vector units offer scope for hardware acceleration of applications. Implementin...