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» Memory Exploration for Low Power, Embedded Systems
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MICRO
2007
IEEE
188views Hardware» more  MICRO 2007»
14 years 4 months ago
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Fal...
ISCA
1997
IEEE
93views Hardware» more  ISCA 1997»
14 years 1 months ago
The Energy Efficiency of IRAM Architectures
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
Richard Fromm, Stylianos Perissakis, Neal Cardwell...
NOSSDAV
2009
Springer
14 years 4 months ago
Power efficient real-time disk scheduling
Hard-disk drive power consumption reduction methods focus mainly on increasing the amount of time the disk is in standby mode (disk spun down) by implementing aggressive data read...
Damien Le Moal, Donald Molaro, Jorge Campello
ITC
2003
IEEE
124views Hardware» more  ITC 2003»
14 years 3 months ago
Power-aware NoC Reuse on the Testing of Core-based Systems
This work discusses the impact of power consumption on the test time of core-based systems, when an available on-chip network is reused as test access mechanism. A previously prop...
Érika F. Cota, Luigi Carro, Flávio R...
ICCAD
1995
IEEE
144views Hardware» more  ICCAD 1995»
14 years 1 months ago
Background memory management for dynamic data structure intensive processing systems
Abstract -- Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently availab...
Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wu...