2078 search results - page 15 / 416 » MetaCores: Design and Optimization Techniques |
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
—1As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concern for circuit designers. On the other hand, r...
VTS
2003
IEEE
14 years 1 months ago
2003
IEEE
1 We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the ai...
DAC
1996
ACM
14 years 18 days ago
1996
ACM
To reduce the number of synthesis and layout iterations, we present a new delay optimization technique, which inserts buers based on back-annotated detailed routing information. D...
INFOCOM
2012
IEEE
11 years 11 months ago
2012
IEEE
Abstract—Although femtocell deployments in residential buildings have been increasingly prevalent, femtocell deployment in commercial building environments remains in its infancy...
SASP
2009
IEEE
14 years 3 months ago
2009
IEEE
—With the appearance of massively parallel and inexpensive platforms such as the G80 generation of NVIDIA GPUs, more real-life applications will be designed or ported to these pl...