58 search results - page 1 / 12 » Minimal Delay Interconnect Design Using Alphabetic Trees |
DAC
1994
ACM
14 years 10 months ago
1994
ACM
Abstract - We propose a new algorithm for the performancedriven interconnect design problem, based on alphabetic trees. The interconnect topology is determined in a global manner a...
DAC
1998
ACM
15 years 7 months ago
1998
ACM
Because magnetic e ects have a much longer spatial range than electrostatic e ects, an interconnect line with large inductance will be sensitive to distant variations in interconn...
INFOCOM
1992
IEEE
14 years 10 months ago
1992
IEEE
This paper describes a methodology for designing interconnected LAN-MAN networks with the objective of minimizing the average network delay. We consider IEEE 802.3-5 LANs intercon...
VLSID
2003
IEEE
15 years 6 months ago
2003
IEEE
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer siz...
EURODAC
1994
IEEE
14 years 10 months ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...